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RASER™: Full Chip Circuit Simulator
Infinisim RASER is the next-generation transistor-level simulation and analysis tool for pre-layout and post-layout verification of integrated circuits.

RASER provides SPICE-accurate transient analysis results with an average of 50X higher throughput and capacity. Using Real-time Adaptive Simulation™ (RAS™) technology, RASER delivers SPICE accuracy at cutting-edge speeds.

Key Applications of RASER™:
Customers use RASER successfully in the following applications where other solutions fall short:

  • Timing Closure for clock path and critical paths
    • For high-speed and small process designs (45nm and below) when static-timing is not accurate enough.

  • Post-layout timing verification including post-layout parasitics.
    • Netlist sizes (> 1 million devices) are too large for existing spice to handle.
    • RASER provides accuracy where "fast-spice" is not accurate enough in order to ensure timing is correct.

  • Timing Verification in dense layouts including capacitive coupling:
    • RASER provides fast and full identification of functionality failures for designs that "work" in pre-layout but fail in post-layout due to capacitively-coupled noise.

  • Yield Analysis:
    • With RASER, designers can do spice-accurate monte-carlo analysis for critical-path timing. Before now, designers either had to rely on corner analysis (which required expensive over-design and risked missing market windows) or static-timing analysis, which failed to provide accurate slew and skew results and therefore unknown yield coverage.

  • Accurate dynamic and static-power analysis:
    • Spice accuracy of large post-layout netlists with RASER provides confidence in switching and static supply currents. These large netlists are usually too large for spice. Fast-spice typically produces unacceptably inaccurate results due to model look-up and relaxed convergence requirements.